Analysis on applicable error-correcting code strength of storage class memory and NAND flash in hybrid storage. (14th February 2018)

• Record Type: Journal Article
• Authors: Matsui, Chihiro; Kinoshita, Reika; Takeuchi, Ken
• Is Part Of: Japanese journal of applied physics. Volume 57:Number 4(2018)Supplement
• Publication Date: 2018-02-14
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.57.04FE01
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: A hybrid of storage class memory (SCM) and NAND flash is a promising technology for high performance storage. Error correction is inevitable on SCM and NAND flash because their bit error rate (BER) increases with write/erase (W/E) cycles, data retention, and program/read disturb. In addition, scaling and multi-level cell technologies increase BER. However, error-correcting code (ECC) degrades storage performance because of extra memory reading and encoding/decoding time. Therefore, applicable ECC strength of SCM and NAND flash is evaluated independently by fixing ECC strength of one memory in the hybrid storage. As a result, weak BCH ECC with small correctable bit is recommended for the hybrid storage with large SCM capacity because SCM is accessed frequently. In contrast, strong and long-latency LDPC ECC can be applied to NAND flash in the hybrid storage with large SCM capacity because large-capacity SCM improves the storage performance.