Impact of crystal orientation on ohmic contact resistance of enhancement-mode p-GaN gate high electron mobility transistors on 200 mm silicon substrates. (14th February 2018) - Van Hove, Marleen; Posthuma, Niels; Geens, Karen; Wellekens, Dirk; Li, Xiangdong; Decoutere, Stefaan
Abstract: p-GaN gate enhancement mode power transistors were processed in a Si CMOS processing line on 200 mm Si(111) substrates using Au-free metallization schemes. Si/Ti/Al/Ti/TiN ohmic contacts were formed after full recessing of the AlGaN barrier, followed by a HCl-based wet cleaning step. The electrical performance of devices aligned to the and the perpendicular directions was compared. The ohmic contact resistance was decreased from 1 Ω·mm for the direction to 0.35 Ω·mm for the direction, resulting in an increase of the drain saturation current from 0.5 to 0.6 A/mm, and a reduction of the on-resistance from 6.4 to 5.1 Ω·mm. Moreover, wafer mapping of the device characteristics over the 200 mm wafer showed a tighter statistical distribution for the direction. However, by using an optimized sulfuric/ammonia peroxide (SPM/APM) cleaning step, the ohmic contact resistance could be lowered to 0.3 Ω·mm for both perpendicular directions.