BDD-Based Topology Optimization for Low-Power DTIG FinFET Circuits. (18th July 2019)

• Record Type: Journal Article
• Authors: Ni, Haiyan; Hu, Jianping; Zhang, Xuqiang; Zhu, Haotian
• Other Names: Ghibaudo Gerard Academic Editor.
• Is Part Of: Active and passive electronic components. Volume 2019(2019)
• Publication Date: 2019-07-18
• Subjects: Electronics -- Periodicals; Passive components -- Periodicals; Electronic apparatus and appliances -- Periodicals; 621.381505
• DOI: 10.1155/2019/8292653
• Languages: English
• ISSNs: 0882-7516

Abstract

Abstract : This paper proposed a logic synthesis method based on binary decision diagram (BDD) representation. The proposed method is optimized for dual-threshold independent-gate (DTIG) FinFET circuits. The algorithm of the BDD-based topology optimization is stated in detail. Some kinds of feature subgraph structures of a BDD are extracted by the extraction algorithm and then fed to mapping algorithm to get a final optimized circuit based on predefined DTIG FinFET logic gates. Some MCNC benchmark circuits are tested under the proposed synthesis method by comparing with ABC, DC tools. The simulations show that the proposed synthesis method can obtain performance improvement for DTIG FinFET circuits.