An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata. (January 2018)

• Record Type: Journal Article
• Authors: Chudasama, Ashvin; Sasamal, Trailokya Nath; Yadav, Jyoti
• Is Part Of: Computers & electrical engineering. Volume 65(2018)
• Page Start: 527
• Page End: 542
• Publication Date: 2018-01
• Subjects: Full adder -- Ripple carry adder -- Majority gate -- Quantum-dot Cellular Automata (QCA) -- Vedic multiplier; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2017.09.019
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies, which yields attractive features like high speed, low power consumption and smaller size for implementing computing architecture in contrast to the CMOS technology. Numerous studies of adders and multiplier have been reported in this direction using QCA. This paper mainly focuses on designing of 8 × 8 Vedic multiplier in QCA using Urdhva Tiryagbhyam sutra. An efficient structure of 4-bit Vedic multiplier is used to construct an 8-bit multiplier. Moreover, the additions of generated partial products are realized using ripple carry adders and full adders. A generalized structure of N × N Vedic multiplier and the complexity of N × N multiplier design is also discussed. All the designs are simulated on QCADesigner tool and it confirms the efficiency of the proposed design. The simulation results show that the proposed design of 8 × 8 Vedic multiplier has reduced 60% cell count, 78% area, and 75% delay as compared to the 8 × 8 Wallace multiplier. In addition, it achieves equal complexity in term of cell count, but delay and area are reduced by 64% and 18% respectively compared to Array I multiplier. Furthermore, a general expression for the number of majority gates, inverters, crossovers, and delay is derived and compared with the Array I and Array II multiplier.