Universal gates on garbled circuit construction. (11th April 2019)

• Record Type: Journal Article
• Authors: Innocent, A. Anasuya Threse; K, Sangeeta; Prakash, G.
• Is Part Of: Concurrency and computation. Volume 31:Number 17(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2019-04-11
• Subjects: Boolean circuit -- garbled circuit construction -- secure computation; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.5236
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: Efficient garbled circuit construction can lead to more practical secure computation protocols. Garbled circuit construction has been considered as a separate goal for optimization as efficiency of the secure computation protocol is directly related to the efficiency of garbled circuit construction. Various optimizations such as, point‐and‐permute technique, free‐XOR, garbled row reduction, and dual‐key cipher are proved to make the garbled circuit construction efficient. In this paper, we propose garbled circuit construction with the universal gates; for demonstration purpose, we have considered NOR gates and shown optimization on circuit construction in two models. By the use of single type of gate, the gate array in the circuit representation is eliminated and a constant value is used in protocols. In addition, we have reduced the number of rows in garbled table to two rows per gate with two or zero encryption calls during garbled circuit construction and two or zero decryption calls during evaluation of garbled circuit.