An efficient implementation of novel Paillier encryption with polar encoder for 5G systems in VLSI. (January 2018)

• Record Type: Journal Article
• Authors: Ganesan, Indumathi; Balasubramanian, Aarthi Alias Ananthakirupa; Muthusamy, Ramesh
• Is Part Of: Computers & electrical engineering. Volume 65(2018)
• Page Start: 153
• Page End: 164
• Publication Date: 2018-01
• Subjects: Paillier encryption -- Polar encoder -- Field programmable gate array -- Hardware utilization -- 5G; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2017.04.026
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: A novel design of Paillier encryption with polar encoding is proposed. A new cross-partitioned add shift processing element is designed for the realization of the Paillier encryption. The proposed processing element is based on perfect reconstruction technique. A modified low complex polar encoder architecture is developed by reformulating the delay requirement. It is followed by optimal placement of register allocation using reduced register delay allocation algorithm. The proposed joint encryption-encoder can be deployed in imminent 5G systems. Graphical abstract: Abstract: In this paper, a novel design of Paillier encryption with a modified polar encoding is proposed and analyzed. A new cross-partitioned add shift processing element based on perfect reconstruction technique is designed for the realization of encryption with proper distribution of adders and shifters to minimize the logical component and register usage. In addition, a modified architecture for the polar encoder with optimal delay/ minimized hardware resource is achieved by presenting a novel delay calculation methodology followed by register allocation grouped as the Reduced Register Delay Allocation (RRDA) algorithm. Resource utilization, including slice registers, lookuptables (LUTs) and DSP blocks are measured along with operating speed and throughput for the proposed paillier encryption and polar encoder. Finally, the performance is analyzed with the existing designs. The proposed sequential encoding-encryption can be deployed in imminent 5G systems.