Real-time physical register file allocation with neural networks for simultaneous multi-threading processors. (5th July 2019)

• Record Type: Journal Article
• Authors: Wang, Wenjun; Lin, Wei-Ming
• Is Part Of: International journal of high performance systems architecture. Volume 8:Number 3(2018)
• Page Start: 146
• Page End: 158
• Publication Date: 2019-07-05
• Subjects: simultaneous multi-threading -- SMT -- register renaming -- physical register file -- neural networks -- machine learning; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

Simultaneous multi-threading (SMT) processors improve system performance by allowing concurrent execution of multiple independent threads with shared key resources. Physical register file, shared among the threads in real-time, is one of the most critical resources in deciding overall system performance. Disproportional distribution of registers among the threads may easily hamper normal processing of some threads. In this paper, we develop a machine learning algorithm to efficiently allocate registers among concurrent executing threads based on current resource utilisation circumstances. An offline training process is first employed to establish a well-trained neural network which is then applied to dynamically adjust the resource distribution in real-time. Our experiment results on M-sim, which is a multi-threaded micro-architectural simulation environment, show that our proposed technique significantly improves the average system throughput by up to 42% without sacrificing execution fairness among the threads.