A design methodology for mobile and embedded applications on FPGA-based dynamic reconfigurable hardware. (20th September 2019)

• Record Type: Journal Article
• Authors: Perera, Darshika G.; Li, Kin Fun
• Is Part Of: International journal of embedded systems. Volume 11:Number 5(2019)
• Page Start: 661
• Page End: 677
• Publication Date: 2019-09-20
• Subjects: design methodology -- mobile applications -- embedded applications -- FPGA-based dynamic reconfigurable hardware -- FPGAs -- mobile devices -- embedded systems -- dynamic reconfiguration -- mapping pipelined computation model to FPGAs -- mapping functional parallel computation model to FPGAs; Embedded computer systems -- Periodicals; 004.16
• Languages: English
• ISSNs: 1741-1068

Abstract

With the proliferation of mobile/embedded devices, multiple running applications are becoming a necessity on these devices. Thus, state-of-the-art techniques are needed to support complex applications running on mobile systems. We envision in the near future, many mobile devices will be implemented/delivered on FPGA-based reconfigurable chips. Previous analysis illustrated that FPGA-based dynamic-reconfigurable-hardware is currently the best option to deliver embedded applications that have stringent requirements. However, computation models and application characteristics play significant roles in determining whether this hardware is indeed a good match for specific embedded applications. Furthermore, selecting a specific dynamic reconfiguration method (out of many) and designing the corresponding hardware architectures for an application are important and challenging tasks. This paper proposes a design methodology for FPGA-based dynamic-reconfigurable-hardware that provides guidelines in mapping application's computation models and characteristics to the most suitable reconfiguration methods. Pipelined and functional-parallel models are used as case studies to illustrate the design methodology.