Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers. (25th September 2019)

• Record Type: Journal Article
• Authors: Mehra, Anu; Verma, Vinay; Majumdar, Rana; Gaur, Nidhi; Kumar, Alok; Awasthi, Ansh; Pandey, Chanda
• Is Part Of: International journal of industrial and systems engineering. Volume 33:Number 2(2019)
• Page Start: 129
• Page End: 140
• Publication Date: 2019-09-25
• Subjects: delay -- look up table -- LUT -- power -- Vedic multiplier; Systems engineering -- Periodicals; Industrial engineering -- Periodicals; 620.001171
• Languages: English
• ISSNs: 1748-5037

Abstract

Multipliers are the basic building blocks of various processors; arithmetic and logical unit and they are widely used in digital signal processing and image processing applications such as convolution, DWT, DCT. In this paper, four separate algorithms for designing binary multipliers are adopted from the ancient Indian Book of Wisdom Sthapatya-veda (an Upa-veda of Atharvaveda) . The current work mainly focuses on comparing the power, delay, look up table (LUT), noise margin of different multiplier algorithms using various sutra's of Vedic mathematics which has been implemented on Virtex 7 Board 1.1, using Xilinx Vivado version 14.2.