Advanced Electron Microscopy for III/V on Silicon Integration. Issue 12 (6th May 2019)

• Record Type: Journal Article
• Authors: Beyer, Andreas; Volz, Kerstin
• Is Part Of: Advanced materials interfaces. Volume 6:Issue 12(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2019-05-06
• Subjects: compound semiconductors -- III/V silicon -- interfaces -- scanning transmission electron microscopy; Materials science -- Periodicals; 620.11
• DOI: 10.1002/admi.201801951
• Languages: English
• ISSNs: 2196-7350

Abstract

Abstract: The combination of III/V semiconductors with Si is very attractive, since it allows the fabrication of high efficient optoelectronic devices like solar cells, lasers or the integration of III/V transistors on Si substrates. However, the growth of polar III/V materials on nonpolar Si holds several challenges. The different valences of group III and group V atoms as well as Si possibly give rise to the formation of charged defects, i.e., antiphase boundaries, as well as to charge accumulation at the interface between the different materials. Accordingly, the interfaces present, i.e., the ones between antiphase and main phase and the one between III/V and Si, eventually limit any device's performance. Electron microscopy, in particular transmission electron microscopy, has proven to be a valuable tool to acquire quantitative information from III/V–Si heterostructures. Among this information are defect densities as well as the structure of the involved interfaces at spatial resolutions down to the atomic level. Moreover, information on charge distribution can be retrieved. In this review, the authors collocate the results gained for the model system GaP on Si utilizing various electron microscopy related techniques. Abstract : The integration of III/V materials on silicon is the basis of many future device concepts. One crucial point is the interface, where the two materials meet. Quantitative transmission electron microscopy shows that the atomically resolved interface is restructured pyramidally to minimize the charge. Defects originating from the interface can be suppressed to finally achieve a perfect III/V layer for further devices.