Are Extended Defects a Show Stopper for Future III-V CMOS Technologies. (May 2019)

• Record Type: Journal Article
• Authors: Claeys, C; Hsu, P-C; He, L; Mols, Y; Langer, R; Waldron, N; Eneman, G; Collaert, N; Heyns, M; Simoen, E
• Is Part Of: Journal of physics. Volume 1190(2019)
• Publication Date: 2019-05
• Subjects: Physics -- Congresses; 530.5
• DOI: 10.1088/1742-6596/1190/1/012001
• Languages: English
• ISSNs: 1742-6588

Abstract

Abstract: The paper briefly reviews some of the present-day state-of-the art III-V devices processed on a Si platform reported in the literature, before addressing defect engineering aspects for III-V processing on a Si substrate from both a structural and electrical performance perspective. The identification of the extended defects will be illustrated by some case studies based on leakage current and lifetime investigations, Deep Level Transient Spectroscopy (DLTS) analysis and low frequency noise spectroscopy. Information on the basic defect parameters can be used as input for TCAD simulation of the electrical device performance, enabling a further optimization of the materials' growth and process conditions.