Investigating the effectiveness of Without Charge-Sharing Quasi-Adiabatic Logic for energy efficient and secure cryptographic implementations. (June 2018)

• Record Type: Journal Article
• Authors: Raghav, Himadri Singh; Bartlett, Viv A.; Kale, Izzet
• Is Part Of: Microelectronics journal. Volume 76(2018)
• Page Start: 8
• Page End: 21
• Publication Date: 2018-06
• Subjects: Power analysis attacks resilient -- Secure adiabatic logic -- Charge sharing -- Energy consumption -- Countermeasure; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.04.004
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Existing secure adiabatic logic designs use charge sharing inputs to deliver input independent energy dissipation and suffer from non-adiabatic losses (NAL) during the evaluation phase of the power-clock. However, using additional inputs present the overhead of generation, scheduling, and routing of the signals. Thus, we present "Without Charge-Sharing Quasi-Adiabatic Logic", WCS-QuAL which doesn't require any charge sharing inputs and completely removes the NAL. The pre-layout and post-layout simulation results of the gates show that WCS-QuAL exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) against all process corner variations at frequencies ranging from 1 MHz to 100 MHz. It also shows least variations in average energy dissipation at all five process corners. The simulation results show that the 8-bit Montgomery multiplier using WCS-QuAL exhibits the least value of NED and NSD at all the simulated frequencies and against power-supply scaling and dissipates the lowest energy at frequencies ranging from 20 MHz to 100 MHz.