A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector. (7th February 2018)

Record Type:: Journal Article
Title:: A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector. (7th February 2018)
Main Title:: A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector
Authors:: Parkalian, N.
Robens, M.
Grewing, C.
Christ, V.
Kruth, A.
Liebau, D.
Muralidharan, P.
Nielinger, D.
Roth, C.
Yegin, U.
Zambanini, A.
van Waasen, S.
Abstract:
Is Part Of:: Journal of instrumentation. Volume 13:Number 2(2018:Feb.)
Journal:: Journal of instrumentation
Issue:: Volume 13:Number 2(2018:Feb.)
Issue Display:: Volume 13, Issue 2 (2018)
Year:: 2018
Volume:: 13
Issue:: 2
Issue Sort Value:: 2018-0013-0002-0000
Page Start:: P02010
Page End:: P02010
Publication Date:: 2018-02-07
Subjects:: Analogue electronic circuits -- Front-end electronics for detector readout -- VLSI circuits
Scientific apparatus and instruments -- Periodicals
502.84
Journal URLs:: http://iopscience.iop.org/1748-0221 ↗
http://ioppublishing.org/ ↗
DOI:: 10.1088/1748-0221/13/02/P02010 ↗
Languages:: English
ISSNs:: 1748-0221
Deposit Type:: Legaldeposit
View Content:: Available online (eLD content is only available in our Reading Rooms) ↗
Physical Locations:: British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store
Ingest File:: 11101.xml