An 11-bit 200 MS/s subrange SAR ADC with low-cost integrated reference buffer *Project supported by the Zhongxing Telecommunication Equipment Corporation and Beijing Microelectronics Technology Institute. (October 2017) - He, Xiuju; Gu, Xian; Li, Weitao; Jiang, Hanjun; Li, Fule; Wang, Zhihua
Abstract: This paper presents an 11-bit 200 MS/s subrange SAR ADC with an integrated reference buffer in 65 nm CMOS. The proposed ADC employs a 3.5-bit flash ADC for coarse conversion, and a compact timing scheme at the flash/SAR boundary to speed up the conversion. The flash decision is used to control charge compensating for the reference voltage to reduce its input-dependent fluctuation. Measurement results show that the fabricated ADC has achieved significant improvement by applying the reference charge compensation. In addition, the ADC achieves a maximum signal-to-noise-and-distortion ratio of 59.3 dB at 200 MS/s. It consumes 3.91 mW from a 1.2 V supply, including the reference buffer.