A custom 70-channel mixed signal ASIC for the brain-PET detectors signal readout and selection. (5th June 2019)

• Record Type: Journal Article
• Authors: Mian Qaisar, Saeed
• Is Part Of: Biomedical physics & engineering express. Volume 5:Number 4(2019)
• Publication Date: 2019-06-05
• Subjects: PET -- ASIC -- photodetectors -- crystal scintillators -- signal selection -- delay line; Medical physics -- Periodicals; Biophysics -- Periodicals; Biomedical engineering -- Periodicals; Medical sciences -- Periodicals; 610.153
• DOI: 10.1088/2057-1976/ab251e
• Languages: English
• ISSNs: 2057-1976

Abstract

Abstract: This paper presents a 70-channel mixed signal Application Specific Integrated Circuit (ASIC) for Silicon Photo-Multipliers (SiPM) detectors, used in the axial architecture based Time of Flight (ToF) Brain-PET scanners, readout. The current pulses obtained at the output of SiPM arrays are transformed into voltages with the help of charge resistances and then passed to the low noise and high bandwidth preamplifier stages. The amplified pulses are simultaneously passed to the pulse detection modules and the low-pass Sallen-Key filtering stages. The cut-off frequency of the filtering stages is selected as 80 MHz. The denoised pulses are conveyed to the discrete times delay lines (DLs). DLs operate at a 200 MHz sampling frequency and are founded on the base of a novel parallel architecture in place of the classical bucket bridge realization. Each detection module sums up the conditioned pulses of the SiPM pair, mutually aligned 180 degrees apart, and compares its mangnitude with a Leading Edge Discriminator (LED). LEDs outputs are employed by the coincidence detection and address encoding module. DLs are parameterized in order to achieve an effective baseline of around 140 ns while properly coping with the processing delays of the pulse detection, the coincidence detection and the address encoding modules. In the case of a coincidence detection, the concerned delayed pulses are selected by piloting two multiplexers with encoded address and are passed to the post processing modules. The selection process avoids the number of false events processing. It improves the sensitivity, processing efficiency and power consumption of the system. The ASIC is implemented on the 0.35 μ m BiCMOS technology. The proposed ASIC functionality is verified with post layout simulations. The typical power consumption is respectively 60.4 mW and 4.693 W for a single channel and for the whole ASIC. Results have confirmed the effectiveness of suggested solution for the SiPM detectors signals readout and selection for Brain-PET applications.