MATRIX: a 15 ps resistive interpolation TDC ASIC based on a novel regular structure. (19th December 2016)

• Record Type: Journal Article
• Authors: Mauricio, J.; Gascón, D.; Ciaglia, D.; Gómez, S.; Fernández, G.; Sanuy, A.
• Is Part Of: Journal of instrumentation. Volume 11:Number 12(2016:Dec.)
• Page Start: C12047
• Page End: C12047
• Publication Date: 2016-12-19
• Subjects: Digital electronic circuits -- Instrumentation and methods for time-of-flight (TOF) spectroscopy -- Timing detectors -- VLSI circuits; Scientific apparatus and instruments -- Periodicals; 502.84
• DOI: 10.1088/1748-0221/11/12/C12047
• Languages: English
• ISSNs: 1748-0221

Abstract

Abstract: This paper presents a 4-channel TDC ASIC with the following features: 15-ps LSB (9.34 ps after calibration), 10-ps jitter, < 4 -ps time resolution, up to 10 MHz of sustained input rate per channel, 45 mW of power consumption and very low area ( 910×215 μ m 2 ) in a commercial 180 nm technology. The main contribution of this work is the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit (patented), a two-dimensional regular structure with very good properties in terms of power consumption, area and low process variability.