Level Zero Trigger processor for the ultra rare kaon decay experiment—NA62. (12th February 2016)

• Record Type: Journal Article
• Authors: Chiozzi, S.; Gamberini, E.; Gianoli, A.; Mila, G.; Neri, I.; Petrucci, F.; Soldi, D.
• Is Part Of: Journal of instrumentation. Volume 11:Number 2(2016:Feb.)
• Page Start: C02037
• Page End: C02037
• Publication Date: 2016-02-12
• Subjects: Digital electronic circuits -- Data acquisition circuits -- Trigger concepts and systems (hardware and software) -- Trigger algorithms; Scientific apparatus and instruments -- Periodicals; 502.84
• DOI: 10.1088/1748-0221/11/02/C02037
• Languages: English
• ISSNs: 1748-0221

Abstract

Abstract: In the NA62 experiment at CERN-SPS the communication between detectors and the Lowest Level (L0) trigger processor is performed via Ethernet packets, using the UDP protocol. The L0 Trigger Processor handles the signals from sub-detectors that take part to the trigger generation. In order to choose the best solution for its realization, two different approaches have been implemented. The first approach is fully based on a FPGA device while the second one joins an off-the-shelf PC to the FPGA. The performance of the two systems will be discussed and compared.