Performance analysis of SOI MOSFET with rectangular recessed channel. (15th February 2016)

• Record Type: Journal Article
• Authors: Singh, M; Mishra, S; Mohanty, S S; Mishra, G P
• Is Part Of: Advances in natural sciences. Volume 7:Number 1(2016)
• Publication Date: 2016-02-15
• Subjects: high-k -- rectangular recessed channel -- short channel effect -- silicon on insulator -- dual material gate; 2.00 -- 2.07 -- 3.02 -- 6.00 -- 6.01; Nanotechnology -- Periodicals; Nanoscience -- Periodicals; 620.5
• DOI: 10.1088/2043-6262/7/1/015010
• Languages: English
• ISSNs: 2043-6254

Abstract

Abstract: In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI, MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.