Generic high resolution PET detector block using 12 × 12 SiPM array. (14th March 2018)

• Record Type: Journal Article
• Authors: Sajedi, Salar; Zeraatkar, Navid; Taheri, Mohsen; Kaviani, Sanaz; Khanmohammadi, Hadi; Sarkar, Saeed; Sabet, Hamid; Ay, Mohammad Reza
• Is Part Of: Biomedical physics & engineering express. Volume 4:Number 3(2018)
• Publication Date: 2018-03-14
• Subjects: positron emission tomography -- silicone photo-multiplier -- readout electronics -- coincidence detection -- SiPM; Medical physics -- Periodicals; Biophysics -- Periodicals; Biomedical engineering -- Periodicals; Medical sciences -- Periodicals; 610.153
• DOI: 10.1088/2057-1976/aaade8
• Languages: English
• ISSNs: 2057-1976

Abstract

Abstract: With the advancement of the Silicon Photomultiplier (SiPM) technology, these devices are becoming the mainstream for use in high resolution PET detectors especially where the compatibility with magnetic field is critical. Large-area SiPM arrays are now widely used in high resolution PET detector modules. The challenges are emerged in the readout and timing circuitry by the increase of pixel density in the area. The application-specific integrated circuits (ASICs) are developed to readout arrays with standard anode/cathode outputs. SiPM detection principle, which produces dark current noise in the inactive pixels, makes the multiplexing techniques more challenging rather than the PMT signals. In this work a new generic PET detector block using SiPM arrays with three outputs (anode, cathode, and fast) is presented which is suitable for applications in small animal, brain, and clinical PET imaging. The block detector accepts a 12 × 12 array with both standard and fast output signals with an overall detector dimension of 50 × 50 mm 2 . A new version of the scrambled crosswire readout (SCR) method was implemented to reduce 144 'fast outputs' to 9 tile signals and 144 standard outputs to 16 energy channels. The tile signals are also used to generate time pickoff information for timing resolution. We implemented time-to-digital converter (TDC) in Xilinx's SPARTAN6 field programmable gate array (FPGA) by using the 64-tap delay line. This low cost chip performs all required processes for position, energy, time, and interface architecture. The attached 24 × 24 LYSO:Ce array with 2 × 2 × 10 mm 3 pixels is imaged and pixels are resolved clearly in the room temperature. The measured energy resolution of the detector block after calibration for all crystal pixels is 12.4% at 511 keV. Also, the coincidence resolving time for two identical modules was measured at 1.85 ns.