A multilevel inverter based on cascade connection of submultilevel units with reduced switch count. (6th May 2019)

• Record Type: Journal Article
• Authors: Sedaghati, Farzad; Majareh, Seyed Hadi Latifi
• Is Part Of: International journal of circuit theory and applications. Volume 47:Number 7(2019)
• Page Start: 1152
• Page End: 1172
• Publication Date: 2019-05-06
• Subjects: cascade connection -- inverter -- multilevel -- submultilevel; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2638
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: In this paper, a multilevel inverter based on cascade connection of new submultilevel inverters is presented. The suggested submultilevel inverter is constructed using series connection of basic switching units. The proposed multilevel inverter uses fewer power switches in comparison with some similar topologies which results in reduction of switch gate drivers and also converter size and cost. The proposed multilevel inverter can be implemented in both symmetric and asymmetric configurations. The multilevel inverter configuration and operation principle are described in detail, and then, design methods of symmetric and asymmetric configurations are given. Determination of the optimal number of basic units and cascaded submultilevel inverters regarding criteria such as number of switches and total blocking voltage (TBV) of switches is studied. Power losses of the proposed multilevel inverter are calculated, and then, its symmetric and asymmetric configurations are compared with each other and also with similar cascaded multilevel inverters in various items. The validity of the suggested cascaded multilevel inverter is verified using both computer simulations and laboratory prototype implementation. Abstract : This paper presents a multilevel inverter that is composed of cascade connection of new submultilevel inverters. The suggested submultilevel inverter is constructed using series‐connected basic switching units. The proposed multilevel inverter uses fewer power switches in comparison with some similar topologies which results in reduction of switch gate drivers and also converter size and cost. The multilevel inverter configuration and operation principle are given in detail, and its symmetric and asymmetric configurations design methods are described.