Evaluation of variability using Schmitt trigger on full adders layout. (September 2018)

• Record Type: Journal Article
• Authors: Moraes, L.B.; Zimpeck, A.L.; Meinhardt, C.; Reis, R.
• Is Part Of: Microelectronics and reliability. Volume 88/90(2018)
• Page Start: 116
• Page End: 121
• Publication Date: 2018-09
• Subjects: Reliability -- Variability -- FinFET -- ASAP -- Full adder -- Schmitt trigger; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2018.07.061
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The aggressive technology and voltage scaling which modern digital circuits are facing introduce a higher influence in metrics, as performance and power consumption, due to process variability. To mitigate that, novel techniques are proposed and tested in the literature. This work analyzes the impact on variability robustness using a technique based on the replacement of full adders internal inverters by Schmitt Triggers. Some works point that the given technique helps to improve the variability robustness at the electrical level. Therefore, analysis has been performed at layout level using the 7 nm FinFET technology node from ASAP7 library and the technique was applied on four full adder designs. Performance, energy and area are taken into account. Results show up to 64.74% and 66.6% improvement in average delay and energy variability robustness, respectively. Highlights: This work investigates a Schmitt Trigger based technique was tested at layout level on four different types of Full Adder. The technique is aimed to improve the circuits robustness to process variability. It has shown up to 66.6% of improvement in average delay and energy variability, respectively. A cost-benefit analysis needs to be done given the performance, power consumption and area penalties. CMOS Mirror Full Adder with ST shows a good cost-benefit given power, delay, area and process robustness.