Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions. (September 2018) - Aguiar, Y.Q.; Wrobel, F.; Autran, J.-L.; Leroux, P.; Saigné, F.; Touboul, A.D.; Pouget, V.
Abstract: For nanometer technologies, SET is increasingly growing in importance in circuit design. Accordingly, different hardening techniques were developed to reduce the Soft-Error Rate. Considering selective node hardening technique based on standard cells, this work evaluates the SET response of logic gates from a Standard-Cell library under heavy ions. Overall, it is observed that the usage of NOR and NAND gates coupled with an output inverter provides reduced SET cross-section and increased threshold LET compared with the standalone OR gate and AND gate, respectively. With the results gathered in this work, circuit designers can implement reliability-aware synthesis algorithms with selective hardening more efficiently to tackle the threat of SET in combinational circuits. Highlights: The reliability of a Boolean function implementation can be improved by selective node hardening based on standard cells Pulse Quenching Effect is highly dependent on the cell input signals Different patterns of collection regions are induced by the input signals, leading to different charge sharing efficiency The NOR gate coupled with an inverter provides lower SET cross-section and increased threshold LET than the OR gate For the NAND+INV study case, the improvements were mainly restricted to low LET particles