Energy‐efficient operation of a network of OpenFlow switches featuring hardware acceleration and frequency scaling. Issue 6 (2nd May 2019)

• Record Type: Journal Article
• Authors: Ghiasian, Ali; Liu, Pengcheng; Wang, Xiaojun; Collier, Martin
• Is Part Of: Transactions on emerging telecommunications technologies. Volume 30:Issue 6(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2019-05-02
• Subjects: Telecommunication -- Periodicals; 384.05
• DOI: 10.1002/ett.3619
• Languages: English
• ISSNs: 2161-5748

Abstract

Abstract: Recent trends in networking include the move to software‐defined networking, wherein "white‐box" OpenFlow switches unburden control plane functions to a server or the cloud, and network function virtualization (NFV), where network functions traditionally implemented by custom hardware are implemented in generic servers. The use of generic x86 servers reduces costs but limits opportunities to enhance performance and minimise energy consumption. Hardware acceleration techniques used in conjunction with NFV retain the latter's advantages of flexibility and scalability, whilst potentially minimising the energy costs associated with achieving performance targets. In this paper, we utilize field‐programmable gate arrays (FPGAs) for hardware acceleration to perform the switching function of OpenFlow switches. We develop a model of power consumption in a network of FPGA‐based OpenFlow switches. The parameters of the model have been determined empirically using live data from measurements. It has been used in formulating a networkwide optimisation problem wherein frequency scaling is used to minimise power consumption in the network. An online packet routing algorithm is proposed to complete the offline optimisation solution. Our results show that energy efficiency is better achieved when each device operates at an intermediate frequency rather than when the optimisation target is to maximise the number of switches or number of links in sleep state. The improvement is 24% and 40%, respectively. These results suggest a new energy‐efficient flow routing strategy whereby hardware acceleration resources will be utilised to improve energy efficiency. Abstract : In this paper, we develop a model of power consumption in a network of FPGA‐based OpenFlow switches. The parameters of the model have been determined empirically using live data from measurements. It has been used in formulating a network wide optimisation problem wherein frequency scaling is used to minimise power consumption in the network. An online packet routing algorithm is proposed to complete the offline optimisation solution. Our results show that energy efficiency is better achieved when each device operates at an intermediate frequency rather than when the optimisation target is to maximise the number of switches or number of links in sleep state.