Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology. (19th November 2009)

• Record Type: Journal Article
• Authors: Weng, Wu-Te; Lee, Yao-Jen; Lin, Horng-Chih; Huang, Tiao-Yuan
• Other Names: Chu Paul K. Academic Editor.
• Is Part Of: International journal of plasma science and engineering. Volume 2009(2009)
• Publication Date: 2009-11-19
• Subjects: Plasma (Ionized gases) -- Periodicals; Plasma engineering -- Periodicals; Plasma (Gaz ionisés) -- Périodiques; Plasmas, Technique des -- Périodiques; Plasma engineering; Plasma (Ionized gases); Electronic journals; Periodicals; 621.044
• DOI: 10.1155/2009/308949
• Languages: English
• ISSNs: 1687-6245

Abstract

Abstract : This study examines the effects of plasma-induced damage (PID) on Hf-based high-k /dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k /metal-gate transistors are more robust against PID than conventionalSiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k /metal-gate CMOS technology.