A Formal Verification Methodology for DDD Mode Pacemaker Control Programs. (1st September 2015)

• Record Type: Journal Article
• Authors: Shuja, Sana; Srinivasan, Sudarshan K.; Jabeen, Shaista; Nawarathna, Dharmakeerthi
• Other Names: Poncino Massimo Academic Editor.
• Is Part Of: Journal of electrical and computer engineering. Volume 2015(2015)
• Publication Date: 2015-09-01
• Subjects: Computer engineering -- Periodicals; Electrical engineering -- Periodicals; 621.3905
• DOI: 10.1155/2015/939028
• Languages: English
• ISSNs: 2090-0147

Abstract

Abstract : Pacemakers are safety-critical devices whose faulty behaviors can cause harm or even death. Often these faulty behaviors are caused due to bugs in programs used for digital control of pacemakers. We present a formal verification methodology that can be used to check the correctness of object code programs that implement the safety-critical control functions of DDD mode pacemakers. Our methodology is based on the theory of Well-Founded Equivalence Bisimulation (WEB) refinement, where both formal specifications and implementation are treated as transition systems. We develop a simple and general formal specification for DDD mode pacemakers. We also develop correctness proof obligations that can be applied to validate object code programs used for pacemaker control. Using our methodology, we were able to verify a control program with millions of transitions against the simple specification with only 10 transitions. Our method also found several bugs during the verification process.