An FPGA Implementation of a Parallelized MT19937 Uniform Random Number Generator. (30th July 2009)

• Record Type: Journal Article
• Authors: Sriram, Vinay; Kearney, David
• Other Names: Leeser Miriam Academic Editor.
• Is Part Of: EURASIP journal on embedded systems. Volume 2009(2009)
• Publication Date: 2009-07-30
• Subjects: Embedded computer systems -- Periodicals; Systèmes enfouis (Informatique); Embedded computer systems; Periodicals; Electronic journals; 006.22
• DOI: 10.1155/2009/507426
• Languages: English
• ISSNs: 1687-3955

Abstract

Abstract : Recent times have witnessed an increase in use of high-performance reconfigurable computing for accelerating large-scale simulations. A characteristic of such simulations, like infrared (IR) scene simulation, is the use of large quantities of uncorrelated random numbers. It is therefore of interest to have a fast uniform random number generator implemented in reconfigurable hardware. While there have been previous attempts to accelerate the MT19937 pseudouniform random number generator using FPGAs we believe that we can substantially improve the previous implementations to develop a higher throughput and more area-time efficient design. Due to the potential for parallel implementation of random numbers generators, designs that have both a small area footprint and high throughput are to be preferred to ones that have the high throughput but with significant extra area requirements. In this paper, we first present a single port design and then present an enhanced 624 port hardware implementation of the MT19937 algorithm. The 624 port hardware implementation when implemented on a Xilinx XC2VP70-6 FPGA chip has a throughput of119.6 × 10 9 32 bit random numbers per second which is more than 17x that of the previously best published uniform random number generator. Furthermore it has the lowest area time metric of all the currently published FPGA-based pseudouniform random number generators.