AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic. (12th November 2009)

• Record Type: Journal Article
• Authors: Levantino, Salvatore; Zanuso, Marco; Madoglio, Paolo; Tasca, Davide; Samori, Carlo; Lacaita, Andrea L.
• Other Names: Saponara Sergio Academic Editor.
• Is Part Of: EURASIP journal on embedded systems. Volume 2010(2010)
• Publication Date: 2009-11-12
• Subjects: Embedded computer systems -- Periodicals; Systèmes enfouis (Informatique); Embedded computer systems; Periodicals; Electronic journals; 006.22
• DOI: 10.1155/2010/175764
• Languages: English
• ISSNs: 1687-3955

Abstract

Abstract : This paper describes the design of an All-Digital Phase Locked Loop (AD-PLL) for wireless applications in the WiMAX 3.3–3.8 GHz bandwidth. The time/digital converter (TDC) sets the in-band noise and it may be responsible for the presence of spurious tones at the PLL output. The TDC is implemented as a delay-locked loop (DLL) to be insensitive to process spreads and it uses a lead-lag phase detector and a digital loop filter to further take advantage of the digital approach. The most important source of spurs is identified in the time skew between counter and TDC in the PLL. This mechanism gives rise to a glitch in the digital feedback signal and spurs in the output spectrum. A simple glitch-corrector logic is described, that completely removes this effect, thus allowing to meet the phase noise specifications. The AD-PLL has been designed in a 90 nm CMOS process.