Cite
HARVARD Citation
Lee, Y. et al. (2009). Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector. EURASIP journal on embedded systems. p. . [Online].
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Lee, Y. et al. (2009). Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector. EURASIP journal on embedded systems. p. . [Online].