A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell. (10th September 2013)

• Record Type: Journal Article
• Authors: Mehrabi, Shima; Faghih Mirzaee, Reza; Navi, Keivan; Hashemipour, Omid
• Other Names: De Los Santos H. J. Academic Editor.; Hopkinson M. Academic Editor.; Kim H. Academic Editor.
• Is Part Of: ISRN electronics. Volume 2013(2013)
• Publication Date: 2013-09-10
• Subjects: Electronics -- Periodicals; Electronics; Electronic journals; Periodicals; 621.381
• DOI: 10.1155/2013/376869
• Languages: English
• ISSNs: 2090-8679

Abstract

Abstract : Dynamic logic is a well-known logic style which is widely used in digital electronics. A mixed dynamic/static full adder cell is presented in this paper with the aim of reaching high efficiency. The midoutputs are obtained from a Multi-output dynamic module. Then, a multiplexer generates final outputs in the static part. Several conventional and state-of-the-art dynamic adders are also surveyed and compared in the paper. All circuits are simulated by HSPICE with 32 nm CNFET technology. The proposed design is the fastest dynamic adder cell. In addition, it has approximately 5% higher efficiency in terms of PDP than the second most high-performance cell, which is DDCVS.