Leakage Power Analysis of Domino XOR Gate. (19th December 2012)

• Record Type: Journal Article
• Authors: Pandey, A. K.; Mishra, R. A.; Nagaria, R. K.
• Other Names: Hopkinson M. Academic Editor.; McGahay V. Academic Editor.
• Is Part Of: ISRN electronics. Volume 2013(2013)
• Publication Date: 2012-12-19
• Subjects: Electronics -- Periodicals; Electronics; Electronic journals; Periodicals; 621.381
• DOI: 10.1155/2013/271316
• Languages: English
• ISSNs: 2090-8679

Abstract

Abstract : Two new XOR gates are proposed. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. Simulation parameters are measured at 25°C and 110°C. First proposed circuit reduces leakage power consumption up to 50% at 25°C and 58% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 14% as compared to standard N-type domino XOR gate. Similarly, second proposed circuit reduces leakage power consumption up to 73% at 25°C and 90% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 39% as compared to standard N-type domino XOR gate.