A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations. (26th March 2012)

• Record Type: Journal Article
• Authors: Postman, Jacob; Chiang, Patrick
• Other Names: Nikolaidis S. Academic Editor.
• Is Part Of: ISRN electronics. Volume 2012(2012)
• Publication Date: 2012-03-26
• Subjects: Electronics -- Periodicals; Electronics; Electronic journals; Periodicals; 621.381
• DOI: 10.5402/2012/916259
• Languages: English
• ISSNs: 2090-8679

Abstract

Abstract : Scaling CMOS process technology continues to enable increased levels of system integration, leading to on-chip communication demands beyond what traditional digital signaling techniques can efficiently provide with sufficient reliability. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, energy, and reliability and provide a review of interconnect reliability considerations. Finally, we provide a case study to evaluate the efficiency of error correcting codes on a state-of-the-art energy-efficient low-swing interconnect.