Write energy reduction of STT-MRAM based multi-core cache hierarchies. Issue 3 (3rd July 2019)

• Record Type: Journal Article
• Authors: Gupta, Yogendra; Bhargava, Lava
• Is Part Of: International journal of electronics letters. Volume 7:Issue 3(2019)
• Page Start: 249
• Page End: 261
• Publication Date: 2019-07-03
• Subjects: STT-MRAM -- cache memory -- write energy -- multi-core systems; Electronics -- Periodicals; Electronics; Periodicals; 621.38105
• DOI: 10.1080/21681724.2018.1482005
• Languages: English
• ISSNs: 2168-1732

Abstract

ABSTRACT: Spin transfer torque magnetoresistive random access memory (STT-MRAM) is a favourable memory technology for on-chip cache hierarchies in multi-core processors. STT-MRAM offers scalability, near zero leakage power, non-volatility, high density, etc., which makes it a good candidate for on-chip cache memory. However, write access latency and write energy consumption in STT-MRAM is relatively high as compared to traditional SRAM which results in high dynamic power consumption as well as performance degradation. In this paper, we have analysed the impact of write buffers on the STT-MRAM-based cache hierarchy. We have tried to optimise the write operations in L1 and L2 cache by exploiting the small static random access memory-based write buffers. The write operations are redirected to the write buffer and not to the L1 cache which mitigates the energy and performance overhead induced by STT-MRAM write operations. Experiment results on PARSEC benchmark show that STT-MRAM-based cache hierarchy improves 90% static energy. But due to large write energy and latency, the dynamic energy of STT-MRAM-based cache is 12.53% higher than the SRAM-based cache hierarchy. The normalised execution time is improved by 19.33% as compared to SRAM-based cache hierarchy.