Influence of Atomic Layer Deposition Temperature on the Electrical Properties of Al/ZrO2/SiO2/4H‐SiC Metal‐Oxide Semiconductor Structures. Issue 13 (30th April 2018) - Król, Krystian; Sochacki, Mariusz; Taube, Andrzej; Kwietniewski, Norbert; Gierałtowska, Sylwia; Wachnicki, Łukasz; Godlewski, Marek; Szmidt, Jan
Abstract : In this paper a ZrO2 /SiO2 /4H‐SiC dielectric system for potential application as gate dielectric for SiC MOSFETs is investigated. An enhanced breakdown performance for this type of dielectric stacks having typical value of critical field of 17 MV cm −1 and reaching a maximum value of 20 MV cm −1 is presented. The observed results are explained based on high‐k layer properties in conjunction with a reduced impact ionization effect in SiO2 layer. Electrical and structural properties of this dielectric stack are measured and analyzed. Growth temperature of atomic layer deposition process seems to be a crucial parameter that influences on layer microstructure and electrical properties such as permittivity of high‐κ layer and critical electric field for all dielectric stacks. Abstract : An ALD deposited ZrO2/SiO2 stacked dielectric layers are used to enhance breakdown field of silicon‐carbide MOS structures. The increase of the critical field (Ecrit) is depending on ALD high‐κ layer growth temperature. Avrage critical field increase is 1.5 times higher than in single layer dielectric reaching ≈20 MV cm −1 for lower deposition temperatures. Structural and electrical measurements indicates that this results are connected to structural changes of high‐κ layer.