Transparency Engineering in Quantum Dot‐Based Memories. Issue 13 (7th May 2018)

• Record Type: Journal Article
• Authors: Arikan, Ismail Firat; Cottet, Nathanaël; Nowozin, Tobias; Bimberg, Dieter
• Is Part Of: Physica status solidi. Volume 215:Issue 13(2018)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2018-05-07
• Subjects: band engineering -- memory -- quantum dots -- resonant tunnel; Solid state physics -- Periodicals; Solids -- Industrial applications -- Periodicals; 530.41
• DOI: 10.1002/pssa.201800018
• Languages: English
• ISSNs: 1862-6300

Abstract

Abstract : Quantum dot (QD) based memories offer new functionalities as compared to present main stream ones by combining the advantages of DRAM (fast access and write/erase time, good endurance) and Flash memories (long storage time). The present storage times in such memories are demonstrated to be several days at room temperature for GaP‐based devices, while write times as short as picoseconds are possible. There exists however a trade‐off between storage time and erase time. To eliminate this trade‐off, resonant tunneling effects in single or double quantum well structures are studied here as a promising approach. The quantum well structures based on GaAs/Al0.9 Ga0.1 As and GaP/AlP quantum wells inserted in QD‐based memories are designed and simulated using a Schrödinger‐Poisson solver and non‐equilibrium Green's functions (NEGF) to calculate the transparency at a given voltage. By choosing the width of the quantum wells, precise positioning of their energy levels allows for transparency engineering. Our simulations show an increase in transparency by at least 7 orders of magnitude at resonance, leading indeed to sufficiently fast erase times, thus solving the trade‐off problem. Abstract : The trade‐off between erase and storage times in quantum dot‐based memories is eliminated by insertion of quantum wells into the structures creating tunneling resonances. In such structures, it is possible to switch transparency between very high and very low values by altering a voltage bias. Hence, fast erase times (∼ns) and long storage times (∼10 y) can be simultaneously achieved.