Experimental setup of stretchable arid dry pad sensors for the signal acquisition fir filter design using Vedic approach. (July 2019) - Prasad, J.; Geetha, D. Mohana; Srinivasan, K.
Highlights: Design of FIR filters which plays a vital role in medical image applications along with Arid-dry pad sensors. It is designed by using adder and Wave pipelined Vedic multiplier. To minimize the setup time violation and path delay of the FIR filter with pad sensors. The FIR Filter is simulated, synthesized using ISE simulator, Xilinx and Altera Quartus II. Abstract: At present in Medical Image processing a hard point to settle any issue with the assistance of Computer collaborator using Arid-dry pad sensor plays a prominent role. Specialist is to investigate the medical diagnosis with the assistance of imaging system such as The CT scan, MRI scan, EEG, Ultrasound technique or any kind of medical images analyzing the system of the patient with the help of images. Design of low power and low delay digital finite-impulse response (FIR) which plays a vital role in medical image applications along with Arid-dry pad sensors. These days, there are numerous versatile applications requiring low power and high throughput than any time in recent memory. In this research the FIR channel framework configuration has turned into a huge execution objective. The Finite Impulse Response (FIR) Filter is the vital segment for planning a medical image processing. The adders and multipliers play an important role in FIR filter while considering these, not only the fast response but also the number of component, area and path delay. The proposed FIR filter is designed by using adder and Wave pipelined Vedic multiplier from the analysis of various adders and multipliers. The Wave pipelined Vedic multiplier performs multiplication process in a hierarchical manner. The work has demonstrated the effectiveness of Urdhva Triyagbhyam– Vedic technique for multiplication which strikes a distinction in the real procedure of increase itself. It empowers parallel age of moderate items, wipes out undesirable increase ventures with zeros and scaled to higher bit levels. Thus, the proposed method can minimize the setup time violation and path delay of the FIR filter with pad sensors. The proposed FIR Filter is simulated, synthesized, calculating power consumption using ISE simulator, Xilinx and Altera Quartus II.