An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing. (8th May 2012)

• Record Type: Journal Article
• Authors: Schmidt, Andrew G.; Kritikos, William V.; Gao, Shanyuan; Sass, Ron
• Other Names: El-Araby Esam Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2012(2012)
• Publication Date: 2012-05-08
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2012/564704
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high-performance computing community which needs to assemble many of these devices into very large scale, parallel computing machines. This paper describes an integrated on-chip/off-chip network that has been implemented on an all-FPGA computing cluster. The system supports MPI-style point-to-point messages, collectives, and other novel communication. Results include the resource utilization and performance (in latency and bandwidth).