Modules for Pipelined Mixed Radix FFT Processors. (22nd March 2016)

• Record Type: Journal Article
• Authors: Sergiyenko, Anatolij; Serhienko, Anastasia
• Other Names: Hübner Michael Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2016(2016)
• Publication Date: 2016-03-22
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2016/3561317
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : A set of soft IP cores for the Winogradr -point fast Fourier transform (FFT) is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm byr times. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.