High level modeling of Dynamic Reconfigurable FPGAs. (17th May 2009)

• Record Type: Journal Article
• Authors: Quadri, Imran Rafiq; Meftali, Samy; Dekeyser, Jean-Luc
• Other Names: Moreno J. Manuel Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2009(2009)
• Publication Date: 2009-05-17
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2009/408605
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : As System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction of new seamless methodologies and tools to handle the SoC codesign aspects. This paper presents a novel SoC co-design methodology based on Model Driven Engineering and the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) standard, permitting us to raise the abstraction levels and allows to model fine grain reconfigurable architectures such as FPGAs. Extensions of this methodology have enabled us to integrate new features such as Partial Dynamic Reconfiguration supported by Modern FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in a graphical language like Unified Modeling Language (UML) and afterwards transformation of these models automatically generate the necessary code for FPGA synthesis.