High-Speed FPGA 10's Complement Adders-Subtractors. (1st February 2010)

• Record Type: Journal Article
• Authors: Bioul, G.; Vazquez, M.; Deschamps, J. P.; Sutter, G.
• Other Names: Todorovich Elías Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2010(2010)
• Publication Date: 2010-02-01
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2010/219764
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : This paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are presented. Then, attention is given to FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 4-input LUTs (Virtex-4, Spartan-3) and 6-input LUTs (Virtex-5) Xilinx FPGA platforms. All designs are presented with the corresponding time performance and area consumption figures. Results have been compared to straight implementations of a decimal ripple-carry adder and an FPGA 2's complement binary adder-subtractor using the dedicated carry logic, both carried out on the same platform. Better time delays have been registered for decimal numbers within the same range of operands.