Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation. (27th August 2008)

• Record Type: Journal Article
• Authors: Ditmar, Johan; McKeever, Steve; Wilson, Alex
• Other Names: Sutter Gustavo Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2008(2008)
• Publication Date: 2008-08-27
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2008/674340
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs.