RP-Ring: A Heterogeneous Multi-FPGA Accelerator. (4th April 2018)

• Record Type: Journal Article
• Authors: Guo, Shuaizhi; Wang, Tianqi; Tao, Linfeng; Tian, Teng; Xiang, Zikun; Jin, Xi
• Other Names: Hübner Michael Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2018(2018)
• Publication Date: 2018-04-04
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2018/6784319
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : To reduce the cost of designing new specialized FPGA boards as direct-summation MOND (Modified Newtonian Dynamics) simulator, we propose a new heterogeneous architecture with existing FPGA boards, which is called RP-ring (reconfigurable processor ring). This design can be expanded conveniently with any available FPGA board and only requires quite low communication bandwidth between FPGA boards. The communication protocol is simple and can be implemented with limited hardware/software resources. In order to avoid overall performance loss caused by the slowest board, we build a mathematical model to decompose workload among FPGAs. The dividing of workload is based on the logic resource, memory access bandwidth, and communication bandwidth of each FPGA chip. Our accelerator can achieve two orders of magnitude speedup compared with CPU implementation.