FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. (29th March 2011)

• Record Type: Journal Article
• Authors: Schumacher, Tobias; Süß, Tim; Plessl, Christian; Platzner, Marco
• Other Names: Prasanna Viktor K. Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2011(2011)
• Publication Date: 2011-03-29
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2011/760954
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : Reconfigurable computers usually provide a limited number of different memory resources, such as host memory, external memory, and on-chip memory with different capacities and communication characteristics. A key challenge for achieving high-performance with reconfigurable accelerators is the efficient utilization of the available memory resources. A detailed knowledge of the memories' parameters is key for generating an optimized communication layout. In this paper, we discuss a benchmarking environment for generating such a characterization. The environment is built on IMORC, our architectural template and on-chip network for creating reconfigurable accelerators. We provide a characterization of the memory resources available on the XtremeData XD1000 reconfigurable computer. Based on this data, we present as a case study the implementation of a 3D image compositing accelerator that is able to double the frame rate of a parallel renderer.