Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. (12th October 2010)

• Record Type: Journal Article
• Authors: Sauvage, Laurent; Nassar, Maxime; Guilley, Sylvain; Flament, Florent; Danger, Jean-Luc; Mathieu, Yves
• Other Names: Torres Lionel Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2010(2010)
• Publication Date: 2010-10-12
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2010/375245
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally gave evidence that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, so far, this gain turned out to be lower for FPGAs than for ASICs. The solutions demonstrated in this article exploit the dual-output of modern FPGAs to achieve a better balance of dual-rail interconnections. However, we expect that an in-depth analysis of routing resources power consumption could still help reduce the interconnect differential leakage.