3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans. (31st August 2010)

• Record Type: Journal Article
• Authors: de Paulo, Vitor; Ababei, Cristinel
• Other Names: Torres Lionel Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2010(2010)
• Publication Date: 2010-08-31
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2010/603059
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : We propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh networks on a separate layer and one or two heterogeneous floorplanning layers. These architectures combine the benefits of compact heterogeneous floorplans and of regular mesh networks. To demonstrate these benefits, a design methodology that integrates floorplanning, routers assignment, and cycle-accurate NoC simulation is proposed. The implementation of the NoC on a separate layer offers an additional area that may be utilized to improve the network performance by increasing the number of virtual channels, buffers size, or mesh size. Experimental results show that increasing the number of virtual channels rather than the buffers size has a higher impact on network performance. Increasing the mesh size can significantly improve the network performance under the assumption that the clock frequency is given by the length of the physical links. In addition, the 3-layer architecture can offer significantly better network performance compared to the 2-layer architecture.