Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions. (10th July 2018)
- Record Type:
- Journal Article
- Title:
- Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions. (10th July 2018)
- Main Title:
- Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions
- Authors:
- Uchevler, Bahram N.
Svarstad, Kjetil - Other Names:
- Cardoso João Academic Editor.
- Abstract:
- Abstract : With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/softwareAbstract : With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform. … (more)
- Is Part Of:
- International journal of reconfigurable computing. Volume 2018(2018)
- Journal:
- International journal of reconfigurable computing
- Issue:
- Volume 2018(2018)
- Issue Display:
- Volume 2018, Issue 2018 (2018)
- Year:
- 2018
- Volume:
- 2018
- Issue:
- 2018
- Issue Sort Value:
- 2018-2018-2018-0000
- Page Start:
- Page End:
- Publication Date:
- 2018-07-10
- Subjects:
- Adaptive computing systems -- Periodicals
Adaptive computing systems
Periodicals
004 - Journal URLs:
- https://www.hindawi.com/journals/ijrc/ ↗
http://bibpurl.oclc.org/web/52810 ↗ - DOI:
- 10.1155/2018/3276159 ↗
- Languages:
- English
- ISSNs:
- 1687-7195
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library HMNTS - ELD Digital store
- Ingest File:
- 10490.xml