Floorplacement for Partial Reconfigurable FPGA-Based Systems. (5th January 2011)

• Record Type: Journal Article
• Authors: Montone, A.; Santambrogio, M. D.; Redaelli, F.; Sciuto, D.
• Other Names: Dasu Aravind Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2011(2011)
• Publication Date: 2011-01-05
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2011/483681
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : We presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength . Our work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities, and wirelength. Task graphs with few externally connected RRs lead to the biggest decrease, while external wirelength in task graphs with many externally connected RRs show lower improvement. The proposed approach results, as also demonstrated in the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven approaches and a highly increased probability of reuse of existing links (90% reduction can be obtained in the best case).