Challenges in Clock Synchronization for On-Site Coding Digital Beamformer. (25th October 2017)

• Record Type: Journal Article
• Authors: Bojja Venkatakrishnan, Satheesh; Alwan, Elias A.; Volakis, John L.
• Other Names: Kalomiros John Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2017(2017)
• Publication Date: 2017-10-25
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2017/7802735
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.