The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. (1st December 2008)

• Record Type: Journal Article
• Authors: Yu, Chi Wai; Lamoureux, Julien; Wilton, Steven J. E.; Leong, Philip H. W.; Luk, Wayne
• Other Names: Sutter Gustavo Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2008(2008)
• Publication Date: 2008-12-01
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2008/736203
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I/O pins should be arranged around all four sides of the FPU; (4) embedded memory should be located between the FPUs; and (5) connecting higher I/O density coarse-grained blocks increases the demand for routing resources. The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used.