An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation. (4th March 2009)

• Record Type: Journal Article
• Authors: Poikonen, Jonne; Laiho, Mika; Paasio, Ari; Koskinen, Lauri; Halonen, Kari
• Other Names: Cabello Ferrer Diego Academic Editor.
• Is Part Of: EURASIP journal on advances in signal processing. Volume 2009(2009)
• Publication Date: 2009-03-04
• Subjects: Signal processing -- Periodicals; Traitement du signal; Signal processing; Periodicals; 621.3822
• DOI: 10.1155/2009/127630
• Languages: English
• ISSNs: 1687-6172

Abstract

Abstract : A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8, 8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations, reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A32 × 32 cell parallel analog test array for reference-shift with a maximum block-size of16 × 16, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 μ m CMOS technology.