Cite
HARVARD Citation
Meloni, P. et al. (2007). Area and Power Modeling for Networks-on-Chip with Layout Awareness. VLSI design. p. . [Online].
This is an interim version of our Electronic Legal Deposit Catalogue-eJournals and eBooks while we continue to recover from a cyber-attack.
Meloni, P. et al. (2007). Area and Power Modeling for Networks-on-Chip with Layout Awareness. VLSI design. p. . [Online].